H83069RF datasheet(138/1003 Pages) RENESAS

138 / 1003 page

Rev. 5.0, 09/04, page 116 of 978

6.2

6.2.1

Bus Width Control Register (ABWCR)

ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW2

R/W

ABW1

R/W

ABW0

R/W

Bit

Modes

1, 3, 5,

and 7

Initial value

Read/Write

Initial value

Read/Write

Modes

2 and 4

When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus

mode: the upper data bus (D

15 to D8) is valid, and port 4 is an input/output port.

When at least one

bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D

15 to

0).

In modes 1, 3, 5, and 7, ABWCR is initialized to H'FF by a reset and in hardware standby

mode. In modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode.

It is not initialized in software standby mode.

Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access

or 16-bit access for the corresponding areas.

Bits 7 to 0

ABW7 to ABW0

Description

Areas 7 to 0 are 16-bit access areas

Areas 7 to 0 are 8-bit access areas

ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip

memory and registers is fixed, and does not depend on ABWCR settings. These settings are

therefore meaningless in the single-chip modes (mode 7).

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