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H83069RF Datasheet(PDF) 170 Page - Renesas Technology Corp |
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H83069RF Datasheet(HTML) 170 Page - Renesas Technology Corp |
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170 / 1003 page ![]() Rev. 5.0, 09/04, page 148 of 978 16-Bit, Three-State-Access Areas Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D 15 to D8) is used in accesses to even addresses and the lower data bus (D 7 to D0) in accesses to odd addresses. Wait states can be inserted. Bus cycle Even external address in area n Valid Invalid Valid High φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note: n = 7 to 0 T1 T2 T3 Undetermined data Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1) (Byte Access to Even Address) |
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