HD64F2144B datasheet(9/546 Pages) RENESAS

9 / 546 page

Rev. 1.00 Jun.24, 2005 Page ix of xxxii

2.7.7

Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................... 50

2.7.8

Memory Indirect—@@aa:8 ................................................................................... 50

2.7.9

Effective Address Calculation ................................................................................ 52

2.8

Processing States.................................................................................................................. 54

2.9

Usage Notes ......................................................................................................................... 56

2.9.1

Note on TAS Instruction Usage .............................................................................. 56

2.9.2

Note on STM/LDM Instruction Usage ................................................................... 56

2.9.3

Note on Bit Manipulation Instructions.................................................................... 56

2.9.4

EEPMOV Instruction.............................................................................................. 58

Section 3 MCU Operating Modes .........................................................................59

3.1

MCU Operating Mode Selection ......................................................................................... 59

3.2

Register Descriptions ...........................................................................................................59

3.2.1

Mode Control Register (MDCR) ............................................................................ 60

3.2.2

System Control Register (SYSCR) ......................................................................... 61

3.2.3

Serial Timer Control Register (STCR) ................................................................... 63

3.3

Operating Mode Descriptions .............................................................................................. 65

3.3.1

Mode 1 .................................................................................................................... 65

3.3.2

Mode 2 .................................................................................................................... 65

3.3.3

Mode 3 .................................................................................................................... 65

3.3.4

Pin Functions in Each Operating Mode .................................................................. 65

3.4

Address Map in Each Operating Mode ................................................................................ 67

Section 4 Exception Handling ...............................................................................69

4.1

Exception Handling Types and Priority ............................................................................... 69

4.2

Exception Sources and Exception Vector Table .................................................................. 70

4.3

Reset .................................................................................................................................... 71

4.3.1

Reset Exception Handling....................................................................................... 71

4.3.2

Interrupts after Reset............................................................................................... 72

4.3.3

On-Chip Peripheral Modules after Reset is Released ............................................. 72

4.4

Interrupt Exception Handling............................................................................................... 73

4.5

Trap Instruction Exception Handling................................................................................... 73

4.6

Stack Status after Exception Handling................................................................................. 74

4.7

Usage Note........................................................................................................................... 75

Section 5 Interrupt Controller ................................................................................77

5.1

Features................................................................................................................................ 77

5.2

Input/Output Pins ................................................................................................................. 79

5.3

Register Descriptions ...........................................................................................................79

5.3.1

Interrupt Control Registers A to C (ICRA to ICRC) .............................................. 80

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