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HD64F2144B Datasheet(PDF) 21 Page - Renesas Technology Corp |
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HD64F2144B Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 546 page  Rev. 1.00 Jun.24, 2005 Page xxi of xxxii Figures Section 1 Overview Figure 1.1 Block Diagram of H8S/2144B ...................................................................................... 3 Figure 1.2 Block Diagram of H8S/2134B ...................................................................................... 4 Figure 1.3 Pin Arrangements of H8S/2144B.................................................................................. 5 Figure 1.4 Pin Arrangements of H8S/2134B.................................................................................. 6 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 23 Figure 2.2 Stack Structure in Normal Mode................................................................................. 23 Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 24 Figure 2.4 Stack Structure in Advanced Mode............................................................................. 25 Figure 2.5 Memory Map............................................................................................................... 26 Figure 2.6 CPU Internal Registers................................................................................................ 27 Figure 2.7 Usage of General Registers .........................................................................................28 Figure 2.8 Stack............................................................................................................................ 29 Figure 2.9 General Register Data Formats (1).............................................................................. 32 Figure 2.9 General Register Data Formats (2).............................................................................. 33 Figure 2.10 Memory Data Formats...............................................................................................34 Figure 2.11 Instruction Formats (Examples) ................................................................................ 47 Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode...................... 51 Figure 2.13 State Transitions ........................................................................................................ 55 Section 3 MCU Operating Modes Figure 3.1 Address Map (1).......................................................................................................... 67 Figure 3.2 Address Map (2).......................................................................................................... 68 Section 4 Exception Handling Figure 4.1 Reset Sequence (Mode 3)............................................................................................72 Figure 4.2 Stack Status after Exception Handling ........................................................................ 74 Figure 4.3 Operation when SP Value is Odd................................................................................ 75 Section 5 Interrupt Controller Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 78 Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, and Registers KMIMR and KMIMRA ........................................................................ 86 Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0................................................................ 88 Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 94 Figure 5.5 State Transition in Interrupt Control Mode 1 .............................................................. 95 Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 97 |
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