Mode Register 1 (MODE1)

Mode Register 2 (MODE2)

TLC59116

Table 3 describes Mode Register 1.

Table 3. MODE1 – Mode Register 1 (Address 00h) Bit Description

BIT

SYMBOL

VALUE

DESCRIPTION

Register auto-increment disabled

7

AI2

R

1

Register auto-increment enabled

Auto-increment bit 1 = 0

6

AI1

R

1

Auto-increment bit 1 = 1

Auto-increment bit 0 = 0

5

AI0

R

1

Auto-increment bit 0 = 1

0

4

SLEEP

R/W

3

SUB1

R/W

1

2

SUB2

R/W

1

1

SUB3

R/W

1

0

0

ALLCALL

R/W

(1)

R = read, W = write

(2)

Default value

(3)

Requires 500

µs maximum for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LED outputs are

not ensured if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 500-

µs window.

(4)

No blinking or dimming is possible when the oscillator is off.

Table 4 describes Mode Register 2.

Table 4. MODE2 – Mode Register 2 (Address 01h) Bit Description

BIT

SYMBOL

VALUE

DESCRIPTION

Enable error status flag

7

EFCLR

R/W

1

Clear error status flag

6:4

R

Reserved

Group control = dimming

5

DMBLNK

R/W

1

Group control = blinking

3

OCH

R/W

1

Outputs change on ACK

2:0

R

Reserved

(1)

R = read, W = write

(2)

Default value

(3)

Change of the outputs at the Stop command allows synchronizing outputs of more than one TLC59116. Applicable to registers from 02h

(PWM0) to 17h (LEDOUT) only.

Copyright © 2008, Texas Instruments Incorporated

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