N × 40 ns

with N = 0 to 255

(PWM register)

256 × 40 ns = 10.24 µs

(97.6 kHz)

M × 256 × 2 × 40 ns

with M = 0 to 255

(GRPPWM register)

Group Dimming Signal

256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)

Resulting Brightness + Group Dimming Signal

Characteristics of the I

Bit Transfer

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

TLC59116

NOTE: Minimum pulse width for LEDn brightness control is 40 ns.

Minimum pulse width for group dimming is 20.48

µs.

When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has two

pulses of the LED Brightness Control signal (pulse width = n × 40 ns, with n defined in the PWMx register).

This resulting Brightness + Group Dimming signal shows a resulting control signal with M = 4 (8 pulses).

Figure 10. Brightness and Group Dimming Signals

serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a

pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus

is not busy.

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high

period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see

Figure 11).

Figure 11. Bit Transfer

Copyright © 2008, Texas Instruments Incorporated

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