ABSOLUTE MAXIMUM RATINGS

(1)

PACKAGE DISSIPATION RATINGS

(1) (2) (3)

TPS54331

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

PACKAGE

SWITCHING FREQUENCY

–40°C to 150°C

8 pin SOIC

570 kHz

TPS54331D

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

The D package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54331DR). See applications section of

data sheet for layout information.

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

VIN

–0.3 to 30

EN

–0.3 to 5

BOOT

38

Input Voltage

V

VSENSE

–0.3 to 3

COMP

–0.3 to 3

SS

–0.3 to 3

BOOT-PH

8

Output Voltage

PH

–0.6 to 30

V

PH (10 ns transient from ground to negative peak)

–5

EN

100

µA

BOOT

100

mA

Source Current

VSENSE

10

µA

PH

9

A

VIN

9

A

Sink Current

COMP

100

µA

SS

200

Electrostatic Discharge (HBM)

2

kV

Electrostatic Discharge (CDM)

500

V

Operating Junction Temperature

–40 to 150

°C

Storage Temperature

–65 to 150

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PACKAGE

THERMAL IMPEDANCE JUNCTION TO

PSEUDO THERMAL IMPEDANCE JUNCTION TO

AMBIENT

TOP

SOIC8

100 °C/W

5 °C/W

(1)

Maximum power dissipation may be limited by overcurrent protection

(2)

distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below

150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more

information.

(3)

Test board conditions:

a. 2 inches x 1.5 inches, 2 layers, thickness: 0.062 inch

b. 2-ounce copper traces located on the top and bottom of the PCB

c. 6 thermal vias located under the device package

2

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