LC074146LP datasheet(13/31 Pages) SANYO

13 / 31 page

LC074146LP

No.A0906-13/31

* Bold letters indicate initial settings.

ADRS

Bit

Name

Init

Description

[7]

MIC_PDX

MIC amplifier circuit, power down

1:OFF (normal operation) 0:ON

[6]

MIC_PWR_PDX

MIC power circuit (MIC_PWR pin), power down

1:OFF (normal operation) 0:ON

[5]

PGA_PDX

PGA circuit, power down

1:OFF (normal operation) 0:ON

[4]

ADC_PDX

ADC circuit, power down

1:OFF (normal operation) 0:ON

[3]

DAC_PDX

DAC circuit, power down

1:OFF (normal operation) 0:ON

[2]

SEL_PDX

Selector (ALC or DAC) circuit, power down 1:OFF (normal operation) 0:ON

[1]

LO_PDX

Line out circuit, power down

1:OFF (normal operation) 0:ON

00h

[0]

SP_PDX

Speaker amplifier circuit, power down

1:OFF (normal operation) 0:ON

[7]

SYNC_CLR

Internal logic clear

1:ON 0:OFF (normal operation)

[5:4]

VREF_BIAS

00b

Reference voltage circuit (VREF pin) setting

00: Power down 11: Normal operation

10: Quick rise to reference voltage 01:IREF ON/VREF OFF

[2]

PLL_PDX

PLL circuit, power down

1:OFF (normal operation) 0:ON

01h

[0]

VD_PDX

Video driver circuit, power down

1:OFF (normal operation) 0:ON

[5:4]

MIC_GAIN

01b

MIC amplifier circuit, gain setting 11: 26dB 10: 20dB 01: 0dB 00: Inhibited

[3]

SEL_GAIN

Selector circuit, gain setting 1: 6dB 0: 0dB

02h

[1:0]

SEL_IN

01b

Selector circuit, input setting 11, 00: Inhibited 10: ALC 01: DAC

[7:5]

ALC_VAL

001b

ALC circuit, ALC value (limiter level) setting

[4:3]

ALC_FA

11b

ALC circuit, attack coefficient setting

03h

[2:0]

ALC_FR

101b

ALC circuit, recovery coefficient setting

[7]

ALC_FULLEN

ALC circuit, full scale detection mode setting 1: ON 0: OFF

[6]

ALC_ZCD

ALC circuit, zerocross timing gain change 1: ON 0: OFF

[5:4]

ALC_ZCDTM

00b

ALC circuit, zerocross detection timeout time setting

[3:2]

ALC_ATLIM

01b

ALC circuit, inter-zerocross attack limit setting

04h

[1:0]

ALC_RWT

10b

ALC circuit, setting wait time when recovery

05h

[5:0]

ALC_VMAX

0Eh

ALC circuit,

PGA(REC)/digital volume (PB) maximum gain setting 0Eh: 0dB

3Fh to 31h: Inhibited, 30h: +34dB to 00h: -14dB, 1dB step

06h

[5:0]

ALC_GAIN

0Eh

ALC circuit, manual mode PGA gain setting 0Eh: 0dB

3Eh to 31h: Inhibited, 30h: +34dB to 00h: -14dB, 1dB step 3Fh: MUTE

[7]

HSF_ON

HSF filter (high frequency shelf filter) attenuation side only

0: OFF 1: ON

[6]

NOTCH_ON

Notch filter

0: OFF 1: ON

[5:4]

WIND_CUT

00b

Wind cut function(HPF f, operation) 11: 400Hz 10: 300Hz 01: 200Hz

00: OFF

[3]

AD_MUTE

ADOUT output mute 0: OFF 1: ON

[2]

FBCLK

BCLK FS setting 0: 64fs 1: 32fs

08h

[1:0]

REC_ALC

PB_ALC

10b

ALC mode setting

10: REC_ALC, PB manual gain

01: PB_ALC, REC manual gain

00/11: ALCOFF, REC, PB manual gain

[4]

ADF_MASTER

ADF circuit, BCLK, LRCLK setting 1: Master mode 0: Slave mode

[3]

ADF_DAC_INV

ADF circuit, DAC input data setting 1: Inverted 0: Non-inverted

[2]

ADF_ADC_INV

ADF circuit, ADC output data setting 1: Inverted 0: Non-inverted

09h

[1:0]

ADF_MODE

00b

ADF circuit, format setting 11, 10: Right-justified 01: Left justified 00: I

0Ah

[1:0]

SEL_USE_DSP

00b

ADC/DAC path select,

11: Inhibited

10: ADC DSP absent, DAC DSP present (ADC

→ADOUT, DAIN→DSP→DAC)

01: Internal loopback (analog input/output) (ADC

→DSP→ADOUT/DAC)

00: ADC DSP present, DAC DSP absent (ADC

→DSP→ADOUT, DAIN→DAC)

[7]

EVR_MUTE

EVR circuit, mute setting

1: ON 0: OFF

0Bh

[6:0]

EVR_GAIN

00h

EVR circuit, gain setting

00h: MUTE 3Fh: 0dB

57h: +12dB to 2Ch: -9.5dB, 0.5dB step

2Bh: -10dB to 0Ch: -41dB, 1.0dB step

0Bh: -42dB to 00h: -64dB, 2.0dB step

Continued on next page

LC074146LP Datasheet(PDF) 13 Page - Sanyo Semicon Device

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