LC074146LP

No.A0906-21/31

Specification Details

• Power save/system reset

When the PDNB pin is set to 0, all the circuits are set to power down mode regardless of the power down settings for

each block. A 0 on the PDNB pin also triggers a system reset.

After the power is first applied, the system must be reset without fail. (Refer to checkpoint (2) on page 30.)

After resetting, the contents of the serial port register are initialized.

The VREF buffer is activated by releasing power down mode by setting the PDNB pin from 0 to 1, and then by

setting VREF_BIAS[1:0] to 01. When VREF_BIAS [1:0] is set to 10, VREF starts. Along with the start of VREF, the

LINE output pin is biased to 1/2VDDA. Once the VREF voltage has stabilized, VREF_BIAS [1:0] must be set to 11

(normal state).

• Microphone (MIC) amplifier

The microphone amplifier has a differential input and a gain of +26dB (typ).

Its gain can also be set to +20 dB or 0 dB by register MGAIN [1:0]. Its input resistance is 70k

Ω (typ). The MICPWR

is a power output pin for the microphone, and its output voltage is 2.3V (typ 0.767*VDDA).

The maximum output current is 20mA.

The microphone amplifier is placed in the power down mode by setting MIC_PDX to 0.

When MIC_PWR_PDX is set to 0, the microphone power supply circuit is placed in the power down mode.

• Recording system automatic level control (ALC)

The amplifier gain of the PGA (Programmable Gain Amplifier) must be automatically adjusted so that the A/D

converter output audio level is setup to the predetermined value. The gain can be varied within a range (maximum) of

-14dB to +34dB.

When using ALC in the recording system, set REC_ALC to 1 and PB_ALC to 0 (recording system ALC mode).

When REC_ALC is set to 0 and PB_ALC is set to 0 (ALC off mode), the PGA is placed in the manual mode, and the

amplifier gain is fixed to the value of the ALC_GAIN register setting.

When PGA_PDX is set to 0, the PGA is placed in the power down mode. During normal use, the state of PGA_PDX

must be switched at the same time as ADC_PDX.

For further details on operation, refer to “Description of ALC/limiter (Automatic Level Control) operation.”

Any of eight recording ALC levels (in 1dB steps from -3dBFS to -10dBFS) can be set using the ALC_VAL register.

• A/D converter

This converts the analog PGA output signals into digital data, which is then output as 16-bit serial audio data. Three

formats are supported: I

incorporated for anti-aliasing.

When ADC_PDX is set to 0, the A/D converter block is placed in the power down mode.

The 100/fs period following the release of the power down mode is the A/D converter initialization period, and the

data are output as 0.

When the power is first applied and when the system clock is switched, the converter must be initialized.

A digital high-pass filter for canceling DC offset is incorporated.

The filter’s cut-off frequency fc is 0.94Hz (at fs=48kHz). 0dBFS is equivalent to 0.6 *VDDA.

• D/A converter

This converts the digital 16-bit serial audio data into analog signals.

Three formats are supported: I

When DAC_PDX is set to 0, the D/A converter block is placed in the power down mode. When the power down

mode is released, the converter is initialized.

When the power is first applied and when the system clock is switched, the converter must be initialized.

0dBFS is equivalent to 0.6 *VDDA.