ADF4350

Rev. 0 | Page 16 of 28

RD2

REFERENCE

DOUBLER

0DISABLED

1

ENABLED

RD1

REFERENCE DIVIDE BY 2

0DISABLED

1ENABLED

CP4CP3

CP2CP1

ICP (mA)

5.1kΩ

00000.31

00010.63

00100.94

00111.25

01001.56

01011.88

01102.19

01112.50

10002.81

10013.13

10103.44

10113.75

11004.06

11014.38

11104.69

11115.00

R10

R9

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

R2

R1

R DIVIDER (R)

00

0

1

1

00

1

0

2

..

.

.

.

..

.

.

.

..

.

.

.

11

0

0

1020

11

0

1

1021

11

1

0

1022

11

1

1

1023

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

L2

L1

M3

M2

M1

RD2

RD1

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4

CP3

CP2 CP1

U6

U5

U4

U3

U2

U1 C3(0) C2(1) C1(0)

CHARGE

PUMP

CURRENT

SETTING

10-BIT R COUNTER

DBR

CONTROL

BITS

MUXOUT

U5

LDP

0

10ns

16ns

U4

PD POLARITY

0NEGATIVE

1

POSITIVE

U3

POWER DOWN

0DISABLED

1

ENABLED

U2

CP

THREE-STATE

0DISABLED

1ENABLED

U1

COUNTER

RESET

0DISABLED

1

ENABLED

D1

DOUBLEBUFFER

R4 DB22-20

0DISABLED

1

ENABLED

U6

LDF

0FRAC-N

1INT-N

M3

M2

M1

OUTPUT

0

0

0

THREE-STATE OUTPUT

00

1

01

0

DGND

0

1

1

R DIVIDER OUTPUT

1

0

0

N DIVIDER OUTPUT

1

0

1

ANALOG LOCK DETECT

1

1

0

DIGITAL LOCK DETECT

1

1

1

RESERVED

L1

L2

NOISE MODE

00

LOW NOISE MODE

0

1

RESERVED

1

0

RESERVED

11

LOW SPUR MODE

LOW

NOISE AND

LOW SPUR

MODES

Figure 26. Register 2 (R2)

C2

C1

CLOCK DIVIDER MODE

0

0

CLOCK DIVIDER OFF

0

1

FAST-LOCK ENABLE

1

0

RESYNC ENABLE

1

1

RESERVED

D12

D11

..........

D2

D1

CLOCK DIVIDER VALUE

0

0

..........

0

0

0

0

0

..........

0

1

1

0

0

..........

1

0

2

0

0

..........

1

1

3

.

.

..........

.

.

.

.

.

..........

.

.

.

.

.

..........

.

.

.

1

1

..........

0

0

4092

1

1

..........

0

1

4093

1

1

..........

1

0

4094

1

1

..........

1

1

4095

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

0

0

F1

0

C2

C1

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

C3(0) C2(1) C1(1)

CONTROL

BITS

12-BIT CLOCK DIVIDER VALUE

CLK

DIV

MODE

F1

CYCLE SLIP

REDUCTION

0DISABLED

1

ENABLED

RESERVED

0

0

Figure 27. Register 3 (R3)