ALU of the DSP core. The YDBx Bus is also con-

nected to the Internal Bus Switch so that it can be

routed to and from other blocks.

3072 X 24-Bit Program RAM

This is a 3072 x 24-Bit Single Port SRAM used

for storing and executing program code. The 16-

Bit PRAM Address, PABx(15:0) is generated by

the Program Address Generator of the DSP core

for Instruction Fetching, and by the AGU in the

case of the Move Program Memory (MOVEM) In-

struction. The 24-Bit PRAM Data (Program

Code), PDBx(23:0), can only be written to using

the MOVEM instruction.

During instruction fetching the PDBx Bus is

routed to the Program Decode Controller of the

DSP core for instruction decoding.

Spare space in the Program area may be used

as data memory to implement delay lines for ex-

ample.

128 x 24-Bit Bootstrap ROM (PROM)

This is a 128 x 24-Bit factory programmed Boot

ROM used for storing the program sequence for

initializing the DSP.

Essentially this consists of a routine that is called

when the DSP comes out of reset. There are

three different boot modes supported by the boot

ROM, one boots directly into PRAM, the second

boots over the I

SPI bus. The boot mode is selected by the levels

on GPIO3 and GPIO5

Serial Audio Interface (SAI)

The SAI is used to deliver digital audio to the

DSPs from an external source. Once processed

by the DSPs, it can be returned through this inter-

face. The features of the SAI are listed below.

Three Synchronized Stereo Data Transmission

Lines

Three Synchronized Stereo Data Reception

Lines

Master/Slave operating modes

Transmit and Receive Interrupt Logic triggers

on Left/Right data pairs

Receive and Transmit Data Registers have

two locations to hold left and right data.

Serial Peripheral Interface

The DSP core requires a serial interface to re-

ceive commands and data over the LAN. During

an SPI transfer, data is transmitted and received

simultaneously. A serial clock line synchronizes

shifting and sampling of the information on the

two serial data lines. A slave select line allows in-

dividual selection of a slave SPI device.

When an SPI transfer occurs an 8-bit word is

shifted out one data pin while another 8-bit char-

acter is simultaneously shifted in a second data

pin.

The central element in the SPI system is the shift

register and the read data buffer. The system is

single buffered in the transfer direction and dou-

ble buffered in the receive direction.

I

The inter Integrated Circuit bus is a single bidirec-

tional two-wire bus used for efficient inter IC con-

trol. All I

an on-chip interface which allows them communi-

cate directly with each other via the I

Every component hooked up to the I

its own unique address whether it is a CPU,

memory or some other complex function chip.

Each of these chips can act as a receiver and /or

transmitter on its functionality.

General Purpose Input/Output

The DSP requires a set of external general pur-

pose input/output lines, and a reset line. These

signals are used by external devices to signal

events to the DSP. The GPIO lines are imple-

mented as DSP ’s peripherals

PLL Clock Oscillator

The PLL Clock Oscillator can accept an external

clock at XTI or it can be configured to run an in-

ternal oscillator when a crystal is connected

across pins XTI & XTO. There is an input divide

block IDF (1 -> 32) at the XTI clock input and a

multiply block MF (33 -> 128) in the PLL loop.

Hence the PLL can multiply the external input

clock by a ratio MF/IDF to generate the internal

clock. This allows the internal clock to be within 1

MHz of any desired frequency even when XTI is

much greater than 1 MHz. It is recommended that

the input clock is not divided down to less than 1

MHz as this reduces the Phase Detector’s update

rate.

The clocks to the DSP can be selected to be

either the VCO output divided by 2 or 4 respec-

tively, or be driven by the XTI pin directly.

The crystal oscillator and the PLL will be gated off

when entering the power-down mode (by setting

bit 1 of the PCON Register).

TDA7502

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