PSD913F2 datasheet(78/91 Pages) STMICROELECTRONICS

78 / 91 page

PSD935G2

PSD9XX Family

-90

-12

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

tLVDV

ALE Access Time from

Power Down

128

135

Maximum Delay from APD Enable

tCLWH

to Internal PDN Valid Signal

Using CLKIN Input

15 * tCLCL (µs) (Note 1)

µs

Power Down Timing (3.0 V to 3.6 V Versions)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tNLNH

Warm RESET Active Low Time (Note 1)

300

tOPR

RESET High to Operational Device

300

tNLNH-PO

Power On Reset Active Low Time

Warm RESETActive Low Time

tNLNH-A

(Note 2)

µs

Reset Pin Timing (3.0 V to 3.6 V Versions)

NOTE: 1. tCLCL is the CLKIN clock period.

Microcontroller Interface – PSD935G2 AC/DC Parameters

(3.0 V to 3.6 V Versions)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tBVBH

Vstby Detection to Vstbyon Output

High

(Note 1)

µs

tBXBL

Vstby Off Detection to Vstbyon

Output Low

(Note 1)

µs

Vstbyon Timing (3.0 V to 3.6 V Versions)

NOTE: 1. RESET will not abort Flash programming/erase cycles.

2. RESET will abort Flash programming or erase cycle.

NOTE: 1. Vstbyon is measured at VCC ramp rate of 2 ms.

PSD913F2 Datasheet(PDF) 78 Page - STMicroelectronics

PSD913F2 Datasheet(HTML) 78 Page - STMicroelectronics

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