LTC2301 datasheet(18/24 Pages) LINER

18 / 24 page

LTC2301/LTC2305

23015f

APPLICATIONS INFORMATION

After power-up, the ADC initiates an internal reset cycle

which sets the DIN word to all 0s (S/D=O/S=UNI=SLP=0).

A write operation may be performed if the default state

of the ADC’s conﬁguration is not desired. Otherwise, the

ADC must be properly addressed and followed by a Stop

condition to initiate a conversion.

Initiating a New Conversion

The LTC2301/LTC2305 awakens from either nap or sleep

when properly addressed for a read/write operation. A

Stop command may then be issued after performing the

read/write operation to trigger a new conversion.

Issuing a Stop command after the 8th SCL clock pulse of

the address frame and before the completion of a read/write

operation will also initiate new conversion, but the output

result may not be valid due to lack of adequate acquisition

time (see Acquisition section).

LTC2301/LTC2305 Address

The LTC2301/LTC2305 have two address pins (AD0 and

AD1) that may be tied high, low or left ﬂoating to enable

one of the 9 possible addresses (see Table 2).

In addition to the conﬁgurable addresses listed in Table 2,

the LTC2301/LTC2305 also contain a global address

(1110111) which may be used for synchronizing multiple

LTC2301/LTC2305s or other I2C LTC230X SAR ADCs (see

Synchronizing Multiple LTC2301/LTC2305s with Global

Address Call section).

Table 2. Address Assignment

AD1

AD0

ADDRESS

LOW

0001000

LOW

FLOAT

0001001

LOW

HIGH

0001010

FLOAT

HIGH

0001011

FLOAT

0011000

FLOAT

LOW

0011001

HIGH

LOW

0011010

HIGH

FLOAT

0011011

HIGH

0101000

Continuous Read

In applications where the same input channel is sampled

each cycle, conversions can be continuously performed

and read without a write cycle (see Figure 8). The DIN word

remains unchanged from the last value written into the

device. If the device has not been written to since power-

up, the DIN word defaults to all 0s (S/D=O/S=UNI=SLP=0).

At the end of a read operation, a Stop condition may be

given to start a new conversion. At the conclusion of the

conversion cycle, the next result may be read using the

method described above. If the conversion cycle is not

concluded and a valid address selects the device, the

LTC2301/LTC2305 generates a NAK signal indicating the

conversion cycle is in progress.

Figure 8. Consecutive Reading with the Same Conﬁguration

CONVERSION

NAP

DATA OUTPUT

CONVERSION

NAP

DATA

OUTPUT

ACK

READ

7-BIT ADDRESS

ACK

23015 F08

READ

7-BIT ADDRESS

LTC2301 Datasheet(PDF) 18 Page - Linear Technology

LTC2301 Datasheet(HTML) 18 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL