Freescale Semiconductor

7

For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,

as shown in Figure 4.

Figure 5. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD

1.1.4

DC Electrical Characteristics

Table 4. DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

Core Supply voltages

• Fsys < 200 MHz

• Fsys < 250 MHz

0.95

1.14

1.0

1.2

1.05

1.26

V

IO Supply voltages

3.14

3.3

3.45

V

Input high voltage

2.0

—

V

Note: To avoid a high current condition and possible system damage, all 3.3-V and 2.5-V supplies must rise before the 1.0-V

supplies rise.

Input low voltage

–0.3

—

0.8

V

Input leakage current

——

± 80

μA

Clock pin Input Capacitance (EXTAL)

—2.057

—

pF

High impedance (off-state) input current (@ 3.3 V or

0V)

–10

—

10

μA

Output high voltage

2.4

—

—

V

Output low voltage

——

0.4

V

Internal pull-up resistor

63

92

142

k

Ω

Internal pull-down resistor

57

91

159

k

Ω

Fsys < 200 MHz

• In Normal mode

—90

280

mA

• In Wait mode

—60

250

mA

Core_VDD

Tr must be < 10 ms

0V

1.0 V

Tr