ADV7181C

Rev. 0 | Page 10 of 20

Pin No.

Mnemonic

Type1

Description

51

RESET

I

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is

required to reset the ADV7181C circuitry.

20

LLC

O

Line-Locked Output Clock. This pin is for the pixel data (the range is

12.825 MHz to 110 MHz).

22

XTAL

I

Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,

28.63636 MHz clock oscillator source to clock the ADV7181C.

21

XTAL1

O

This pin should be connected to the 28.63636 MHz crystal or left as a no connect if

an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the

ADV7181C. In crystal mode, the crystal must be a fundamental crystal.

30

ELPF

O

The recommended external loop filter must be connected to this ELPF pin.

9

SFL/SYNC_OUT

O

SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that

can be used to lock the subcarrier frequency when this decoder is connected

to any Analog Devices digital video encoder.

SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.

41

REFOUT

O

Internal Voltage Reference Output. See Figure 5 for a recommended capacitor

network for this pin.

42

CML

O

Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 5 for a

recommended capacitor network for this pin.

38, 39

CAPY1, CAPY2

I

ADC Capacitor Network. See Figure 5 for a recommended capacitor network for

this pin.

44

CAPC2

I

ADC Capacitor Network. See Figure 5 for a recommended capacitor network for

this pin.

56

HS_IN/CS_IN

I

This pin can be configured in CP mode to be either a digital HS input signal or a

digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.

55

VS_IN

I

VS Input Signal. Used in CP mode for 5-wire timing mode.

50

SOG/SOY

I

Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.

29

PWRDWN

I

A Logic 0 on this pin places the ADV7181C in a power-down mode.

33, 45

NC

No Connect. These pins are not connected internally.