LPC2468 datasheet(2/72 Pages) NXP

2 / 72 page

LPC2468_4

Product data sheet

Rev. 04 — 17 October 2008

2 of 72

NXP Semiconductors

LPC2468

Fast communication chip

N 16 kB SRAM for general purpose DMA use also accessible by the USB.

N 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain.

I Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet

DMA, USB DMA, and program execution from on-chip ﬂash with no contention.

I EMC provides support for asynchronous static memory devices such as RAM, ROM

and ﬂash, as well as dynamic memories such as Single Data Rate SDRAM.

I Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.

I General Purpose AHB DMA controller (GPDMA) that can be used with the SSP,

I2S-bus, and SD/MMC interface as well as for memory-to-memory transfers.

I Serial Interfaces:

N Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

N USB 2.0 full-speed dual port Device/Host/OTG Controller with on-chip PHY and

associated DMA controller.

N Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

N CAN controller with two channels.

N SPI controller.

N Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA

controller.

N Three I2C-bus interfaces (one with open-drain and two with standard port pins).

N I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

I Other peripherals:

N SD/MMC memory card interface.

N 160 General purpose I/O pins with conﬁgurable pull-up/down resistors.

N 10-bit ADC with input multiplexing among 8 pins.

N 10-bit DAC.

N Four general purpose timers/counters with 8 capture inputs and 10 compare

outputs. Each timer block has an external count input.

N Two PWM/timer blocks with support for three-phase motor control. Each PWM has

an external count inputs.

N RTC with separate power domain, clock source can be the RTC oscillator or the

APB clock.

N 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

N WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

I Standard ARM test/debug interface for compatibility with existing tools.

I Emulation trace module supports real-time trace.

I Single 3.3 V power supply (3.0 V to 3.6 V).

I Three reduced power modes: idle, sleep, and power-down.

I Four external interrupt inputs conﬁgurable as edge/level sensitive. All pins on port 0

and port 2 can be used as edge sensitive interrupt sources.

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