LPC2468 datasheet(36/72 Pages) NXP

36 / 72 page

LPC2468_4

Product data sheet

Rev. 04 — 17 October 2008

36 of 72

NXP Semiconductors

LPC2468

Fast communication chip

7.18.1 Features

• The MCI provides all functions speciﬁc to the SD/MMC memory card. These include

the clock generation unit, power management control, and command and data

transfer.

• Conforms to Multimedia Card Speciﬁcation v2.11.

• Conforms to Secure Digital Memory Card Physical Layer Speciﬁcation, v0.96.

• Can be used as a multimedia card bus or a secure digital memory card bus host. The

SD/MMC can be connected to several multimedia cards or a single secure digital

memory card.

• DMA supported through the GPDMA controller.

7.19 I2C-bus serial I/O controller

The LPC2468 contains three I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line

(SCL), and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus and can

be controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2468 supports bit rates up to 400 kbit/s (Fast I2C-bus).

7.19.1 Features

• I2C0 is a standard I2C compliant bus interface with open-drain pins.

• I2C1 and I2C2 use standard I/O pins and do not support powering off of individual

devices connected to the same bus lines.

• Easy to conﬁgure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

7.20 I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio applications.

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