PCA9541_6

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 11 September 2008

17 of 43

NXP Semiconductors

PCA9541

[1]

Default values are the same for PCA9541/01, PCA9541/02, and PCA9541/03.

[2]

Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if:

INT_IN lines goes HIGH for INTIN bit

TESTON bit is cleared for MYTEST bit

NTESTON bit is cleared for NMYTEST bit

[3]

Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master.

[4]

BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register get cleared after a read of the same register is done. Precisely, the

register gets cleared on the second clock pulse during the read operation.

[5]

If the interrupt condition remains on INT_IN after the read sequence, another interrupt will be generated (if the interrupt has not been

masked).

8.5 Power-on reset

internal registers are initialized to their default states, with:

Channel 0 and the downstream slave channel are connected together.

Channel 0 and the downstream slave channel are connected together after a STOP

condition has been detected by the PCA9541/02 on Channel 0.

– If the bus was not idle, Channel 0 and the downstream slave device will be

connected together as soon as a STOP condition occurs at the conclusion of the

transmission sequence on Channel 0.

– If the bus was idle, then Channel 0 is connected to the downstream slave channel

may not be addressed to the PCA9541/02.

– If a switch to Channel 1 (initiated by the master on Channel 1) is requested (before

or after the default switch to Channel 0 has been performed), the upstream

Channel 1 is connected to the downstream slave channel when the master located

in Channel 1 sends the STOP command.

2

BUSOK[4]

R only

0*

no interrupt generated by bus sensor function

1

interrupt generated by bus sensor function (masked when bus

recovery/initialization requested) - Bus was not idle when the switch occurred

1

BUSINIT[4]

R only

0*

no interrupt generated by the bus recovery/initialization function

1

interrupt generated by the bus recovery/initialization function;

recovery/initialization done

0

INTIN[2]

R only

0*

no interrupt on interrupt input (INT_IN)[5]

1

interrupt on interrupt input (INT_IN)[5]

Table 14.

Legend: * default value

Bit

Symbol