PCA9550_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 13 October 2008

4 of 26

NXP Semiconductors

PCA9550

6.

Functional description

Refer to Figure 1 “Block diagram of PCA9550”.

6.1 Device address

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9550 is shown in Figure 5. To conserve power, no

internal pull-up resistor is incorporated on the hardware selectable address pin and it must

be pulled HIGH or LOW.

The last bit of the address byte defines the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9550, which will be stored in the Control register.

The lowest 3 bits are used as a pointer to determine which register will be accessed.

If the Auto-Increment (AI) flag is set, the three low order bits of the Control register are

automatically incremented after a read or write. This allows the user to program the

registers sequentially. The contents of these bits will rollover to ‘000’ after the last register

is accessed.

When the Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the

sequence must start by reading a register different from the input register

(B2 B1 B0

≠ 000).

Only the 3 least significant bits are affected by the AI flag. Unused bits must be

programmed with zeroes.

Fig 5.

PCA9550 slave address

002aad242

1

1

0

0

0

0

A0 R/W

fixed

slave address

hardware

selectable

Reset state: 00h

Fig 6.

Control register

002aad243

0

0

0

AI

0

B2

B1

B0

register address

Auto-Increment flag