CS42888-CQZ datasheet(25/61 Pages) CIRRUS

25 / 61 page

DS717F2

CS42888

The ADC output data is in 2’s complement binary format. For inputs above positive full scale or below neg-

ative full scale, the ADC will output 7FFFFFH or 800000H, respectively, and cause the ADC Overflow bit

in the register “Status (Address 19h) (Read Only)” on page 49 to be set to a ‘1’.

4.2.2

High-Pass Filter and DC Offset Calibration

The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the

corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-

sult. This feature makes it possible to perform a system DC offset calibration by:

Running the CS42888 with the high-pass filter enabled until the filter settles. See the Digital Filter

Characteristics for filter settling time.

Disabling the high-pass filter and freezing the stored DC offset.

The high-pass filter for ADC1/ADC2 can be enabled and disabled. The high-pass filters are controlled us-

ing the HPF_FREEZE bit in the register “ADC Control & DAC De-Emphasis (Address 05h)” on page 44.

4.3

Analog Outputs

4.3.1

Initialization

The initialization and Power-Down sequence flow chart is shown in Figure 11 on page 26. The CS42888

enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma

modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog

and analog-to-digital converters and switched-capacitor low-pass filters are powered down.

The device remains in the power-down state until the RST pin is brought high. The control port is acces-

sible once RST is high, and the desired register settings can be loaded per the interface descriptions in

the “Control Port Description and Timing” on page 33.

VQ will quickly charge to VA/2 upon initial power up. Once MCLK is valid and the PDN bit is set to ‘0’b,

the internal voltage reference, FILT+_ADC and FILT+_DAC, will ramp up to approximately VA. Power is

applied to the D/A converters and switched-capacitor filters, and the analog outputs are clamped to the

quiescent voltage, VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to

determine the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal op-

eration begins.

Full-Scale Differential Input Level =

(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS

AINx+

AINx-

3.9 V

2.5 V

1.1 V

5.0 V

3.9 V

2.5 V

1.1 V

Figure 10. Full-Scale Input

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