CS42888-CQZ datasheet(34/61 Pages) CIRRUS

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DS717F2

CS42888

4.7.1

SPI Mode

In SPI Mode, CS is the CS42888 chip-select signal, CCLK is the control port bit clock (input into the

CS42888 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the

output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling

edge.

Figure 22 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The

first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-

cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),

which is set to the address of the register that is to be updated. The next eight bits are the data which will

be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z

state. It may be externally pulled high or low with a 47 k

Ω resistor, if desired.

There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,

the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment

after each byte is read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which

finishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not,

as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.

The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high

impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear

consecutively.

4.7.2

I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.

There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should

be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the

CS42888 is being reset.

The signal timings for a read and write cycle are shown in Figure 23 and Figure 24. A Start condition is

defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while

the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the

CS42888 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low

for a write). The upper 5 bits of the 7-bit address field are fixed at 10010. To communicate with a CS42888,

the chip address field, which is the first byte sent to the CS42888, should match 10010 followed by the

settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the

MA P

MSB

LSB

DATA

by te 1

by te n

R/W

AD D R ESS

CH IP

ADDRESS

CH I P

CD IN

CC L K

CD O U T

MSB

LSB MSB

LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 22. Control Port Timing in SPI Mode

CS42888-CQZ Datasheet(PDF) 34 Page - Cirrus Logic

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