4141J–AERO–04/07

Features

9301/049

Description

The M67204H implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The expansion logic allows unlimited expansion in word size and depth with no

timing penalties. Twin address pointers automatically generate internal read and write

addresses, and no external address information is required for the Atmel FIFOs.

address pointers are automatically incremented with the write pin and read pin. The 9

bits wide data are used in data communications applications where a parity bit for

error checking is necessary. The retransmit pin reset the read pointer to zero without

affecting the write pointer. This is very useful for retransmitting data when an error is

detected in the system.

Using an array of eight transistors (8T) memory cell, the M67204H combines an

extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns

over the full temperature range. All versions offer battery backup data retention capa-

bility with a typical power consumption at less than 2 µW.

The M67204H is processed according to the methods of the latest revision of the MIL

PRF 38535 (Q and V) or ESCC 9000.

Rad. Tolerant

High Speed

4 Kb x 9

Parallel FIFO

M67204H