16

6396A–DRMSD–15-Oct-08

ATSAM2533

10. Reset and Power-down

During power-up, the RESET input should be held low until the crystal oscillator and PLL are

stabilized, which can take about 20ms.

After the low to high transition of RESET, following happens:

• The Synthesis/DSP enters an idle state.

• P16 program execution starts from address 0100H in ROM space (WCS low).

If PDWN is asserted low and VD18 connected to OUTVC18, then the crystal oscillator and PLL

will be stopped. The chip enters a deep power down sleep mode, as power is removed from the

core. To exit power down, PDWN has to be asserted high, then RESET applied.

11. Recommended Crystal Compensation

Figure 11-1.

Recommended Crystal Compensation