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LT1715

1715fa

The second step is to recalculate R2 to set the same av-

erage threshold as before. The average threshold before

was set at VTH = (VREF)(R1)/(R1 + R2). The new R2 is

calculated based on the average output voltage (+VS/2)and

the simpliﬁed circuit model in Figure 7. To assure that the

comparator’s noninverting input is, on average, the same

VTH as before:

R2´ = (VREF – VTH)/(VTH/R1 + (VTH – VS/2)/R3)

For additional hysteresis of 10mV or less, it is not uncom-

mon for R2´ to be the same as R2 within 1% resistor

tolerances.

This method will work for additional hysteresis of up to

a few hundred millivolts. Beyond that, the impedance of

R3 is low enough to effect the bias string, and adjust-

ment of R1 may also be required. Note that the currents

through the R1/R2 bias string should be many times the

input currents of the LT1715. For 5% accuracy, the cur-

rent must be at least 20 times the input current, more for

higher accuracy.

Interfacing the LT1715 to ECL

The LT1715’s comparators can be used in high speed ap-

plications where Emitter-Coupled Logic (ECL) is deployed.

To interface the output of the LT1715 to ECL logic inputs,

standard TTL/CMOS to ECL level translators such as the

10H124, 10H424 and 100124 can be used. The secom-

ponents come at a cost of a few nanoseconds additional

delay as well as supply currents of 50mA or more, and

are only available in quads. A faster, simpler and lower

power translator can be constructed with resistors as

shown in Figure 8.

Figure 8a shows the standard TTL to Positive ECL (PECL)

resistive level translator. This translator cannot be used

forthe LT1715, or with CMOS logic, because it depends

on the 820Ω resistor to limit the output swing (VOH) of

the all-NPNTTL gate with its so-called totem-pole output.

The LT1715is fabricated in a complementary bipolar

process and the output stage has a PNP driver that pulls

the output nearly all the way to the supply rail, even when

sourcing 10mA.

Figure 8b shows a three resistor level translator for inter-

facing the LT1715 to ECL running off the same supply rail.

No pull-down on the output of the LT1715 is needed, but

pull-down R3 limits the VIH seen by the PECL gate. This

is needed because ECL inputs have both a minimum and

maximum VIH speciﬁcation for proper operation. Resis-

tor values are given for both ECL interface types; in both

cases it is assumed that the LT1715 operates from the

same supply rail.

Figure 8c shows the case of translating to PECL from

an LT1715 powered by a 3V supply rail. Again, resistor

values are given for both ECL interface types. This time

four resistors are needed, although with 10KH/E, R3 is not

needed. In that case, the circuit resembles the standard

TTL translator of Figure 8a, but the function of the new

resistor, R4, is much different. R4 loads the LT1715 output

when high so that the current ﬂowing through R1 doesn’t

forward bias the LT1715’s internal ESD clamp diode.

Although this diode can handle 20mA without damage,

normal operation and performance of the output stage can

be impaired above 100μA of forward current. R4 prevents

this with the minimum additional power dissipation.

Finally, Figure 8d shows the case of driving standard,

negative-rail, ECL with the LT1715. Resistor values are

given for both ECL interface types and for both a 5V

and 3V LT1715 supply rail. Again, a fourth resistor, R4

is needed to prevent the low state current from ﬂowing

out of the LT1715, turning on the internal ESD/substrate

diodes. Resistor R4 again prevents this with the minimum

additional power dissipation.

APPLICATIONS INFORMATION

Figure 7. Model for Additional Hysteresis Calculations

–

1/2 LT1715

1715 F07

R2´

VREF

VTH

+VS

VAVERAGE =

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