2

HV507

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Clock frequency

8

MHz

Clock width high and low

62

ns

t

SU

Data setup time before clock rises

35

ns

Data hold time after clock rises

30

ns

t

WLE

Width of latch enable pulse

80

ns

t

DLE

LE delay time after rising edge of clock

35

ns

LE setup time before rising edge of clock

40

ns

t

Time from latch enable to HV

OUT

4

t

DHL

Delay time clock to data out high to low

125

ns

C

Delay time clock to data out low to high

125

ns

t

All logic inputs

5

ns

Note:

1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec.

Symbol

Parameter

Min

Typ

Max

Units

Conditions

15

mA

LE = LOW

I

DDQ

Quiescent V

200

µA

All V

High voltage supply current

0.50

mA

0.50

mA

I

IH

High-level logic input current

10

Low-level logic input current

-10

High-level output

265

V

Data out

V

V

ID

Low-level output

35

V

Data out

1.0

V

V

OC

HV

V

V

I

-30

V

Symbol

Parameter

Min

Typ

Max

Units

Logic supply voltage

4.5

5.0

5.5

V

V

PP

High voltage supply

60

300

V

V

IH

High-level input voltage

V

V

DD

V

Low-level input voltage

0

0.9

V

T

A

Operating free-air temperature

0

+70

°C

Notes:

Power-up sequence should be the following:

1. Connect ground.

3. Set all inputs (Data, CLK, Enable, etc.) to a known state.

Power-down sequence should be the reverse of the above.

DC Characteristics

Recommended Operating Conditions