4

HV507

•

•

•

60 Additional

Outputs

•

•

•

POL

BL

LE

CLK

64-bit

Static Shift

Register

64 Latches

DIR

L/T

L/T

L/T

L/T

Functional Block Diagram

Inputs

Outputs

Function

Shift Reg

HV Outputs

Data Out

12…64

1

2…64

*

All on

X

X

X

L

L

X

*

*…*H

H…H*

All off

X

X

X

L

H

X

*

*…*L

L…L*

Invert mode

X

X

L

H

L

X

*

*…**

*…**

Load S/R

H or L

↑

LH

H

X

H or L *…**

*…**

Store data

XX

↓

HH

X

*

*…**

*…**

in latches

XX

↓

HL

X

*

*…**

*…**

Transparent

L

↑

HHH

X

L

*…*L

*…**

latch mode

H

↑

HHH

X

H

*…*H

*…**

D

IOA

↑

XXX

L

Q

Q

n-1

—D

IOB

D

IOB

↑

XXX

H

Q

Q

n+1

—D

IOA

Notes:

H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition.

* = dependent on previous stage’s state before the last CLK or last LE high.

Data

CLK

LE

BL

POL

DIR

I/O relation

Function Table

L/T = Level Translator