5

HV583

Pad Description

Vpp

High voltage supply for outputs.

Vdd

Low voltage logic supply

D1A to D4A

Right data input/output. Input when Dir=H, Output when Dir=L.

D1B to D4B

Left data input/output. Input when Dir=L, Output when Dir=H.

Dir

Dir=L or open, D

Clk

Clock input. Data shifted from low to high transition.

RST

Resets latches.

LE

Latch enable. Data latches during rising edge LE.

OE

Output enable bar. HVout high impedance control.

OL

Output low bar. HVout=low when this pin is low.

OH

OH bar input.

DGND

Digital logic ground.

PGND

HVout output ground.

HVout0 to HVout127

High voltage outputs.

Pad Location

PGND

PGND