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HV7224 Datasheet(PDF) 2 Page - Supertex, Inc |
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HV7224 Datasheet(HTML) 2 Page - Supertex, Inc |
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2 / 7 page ![]() 2 Symbol Parameter Min Max Units Conditions IDD VDD supply current 10 mA fCLK = 3MHz I PP High voltage supply current 2.0 mA Outputs low or High-Z 4.0 mA One Output High1 I DDQ Quiescent V DD supply current 100 µA All V IN = GND or VDD VOH High-level output HVOUT 190 V IO= -70mA Data out 4.5 V IO= -100µA V OL Low-level output HV OUT 50 V I O= 70mA Data out 0.5 V IO= 100µA IIH High-level logic input current 1.0 µAVIH = VDD I IL Low-level logic input current -1.0 µAVIL = 0V ISAT Saturation current HVOUT P-Ch -80 mA N-Ch 75 mA Note: 1. Only one output can be turned on at a time. Electrical Characteristics (over recommended operating conditions of V DD = 5V, VPP = 240V, and TA = 25°C unless noted) DC Characteristics Symbol Parameter Min Max Units Conditions fCLK Clock frequency 3.0 MHz t W (H/L) Pulse width - clock high or low 150 ns t SUD Data set-up time before clock rises 50 ns tHD Data hold time after clock rises 50 ns t SUC HV OUT delay from clock rises (Hi-Z to H or L) 1.0 µsCL = 330pF // RL = 10kΩ t SUE HV OUT delay from Output Enable falls 600 ns C L = 330pF // RL = 10kΩ tHC HVOUT delay from clock rises (H or L to Hi-Z) 2.0 µsCL = 330pF // RL = 10kΩ t HE HV OUT delay from Output Enable rises 600 ns C L = 330pF // RL = 10kΩ t DHL * Delay time clock to data output falls 250 ns C L = 15pF tDLH * Delay time clock to data output rises 250 ns CL = 15pF t ONF HV OUT fall time 2.0 µsCL = 330pF // RL = 10kΩ t ONR HV OUT rise time 2.0 µsCL = 330pF // RL = 10kΩ tPOW POL pulse width 3.0 µs t OEW Output Enable pulse width 3.0 µs Slew rate, V PP or GND 45 V/µs One active output driving 4.7nF load AC Characteristics * The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is equal to t WH. Therefore the delay is measured from the trailing edge of the clock. HV7224 |
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