LT1812CS8 datasheet(12/16 Pages) LINER

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LT1812

junction temperature (TJ) is calculated from the ambient

temperature (TA) and power dissipation (PD) as follows:

TJ = TA + (PD • θJA) (Note 9)

Power dissipation is composed of two parts. The first is

due to the quiescent supply current and the second is due

to on-chip dissipation caused by the load current. The

worst-case load induced power occurs when the output

voltage is at 1/2 of either supply voltage (or the maximum

swing if less than 1/2 supply voltage). Therefore PDMAX is:

PDMAX = (V + – V –)(ISMAX) + (V +/2)2/RL or

PDMAX = (V + – V –)(ISMAX) + (V + – VOMAX)(VOMAX/RL)

Example: LT1812CS5 at 70

°C, VS = ±5V, RL = 100Ω

PDMAX = (10V)(4.5mA) + (2.5V)2/100Ω = 108mW

TJMAX = 70°C + (108mW)(250°C/W) = 97°C

Circuit Operation

The LT1812 circuit topology is a true voltage feedback

amplifier that has the slewing behavior of a current feed-

back amplifier. The operation of the circuit can be under-

stood by referring to the Simplified Schematic. The inputs

are buffered by complementary NPN and PNP emitter

followers that drive a 300

Ω resistor. The input voltage

appears across the resistor generating currents that are

mirrored into the high impedance node. Complementary

followers form an output stage that buffers the gain node

from the load. The bandwidth is set by the input resistor

and the capacitance on the high impedance node. The slew

rate is determined by the current available to charge the

gain node capacitance. This current is the differential input

voltage divided by R1, so the slew rate is proportional to

the input. Highest slew rates are therefore seen in the

lowest gain configurations. The RC network across the

output stage is bootstrapped when the amplifier is driving

a light or moderate load and has no effect under normal

operation. When driving capacitive loads (or a low value

resistive load) the network is incompletely bootstrapped

and adds to the compensation at the high impedance

node. The added capacitance slows down the amplifier

which improves the phase margin by moving the unity-

gain cross away from the pole formed by the output

impedance and the capacitive load. The zero created by the

RC combination adds phase to ensure that the total phase

lag does not exceed 180 degrees (zero phase margin) and

the amplifier remains stable. In this way, the LT1812 is

stable with up to 1000pF capacitive loads in unity gain, and

even higher capacitive loads in higher closed-loop gain

configurations.

1812 SS

OUT

+IN

–IN

BIAS

CONTROL

V+

V–

SHDN

300

Ω

SCHEMATIC

SI PLIFIED

APPLICATIO S I FOR ATIO

LT1812CS8 Datasheet(PDF) 12 Page - Linear Technology

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