TC14433COG datasheet(4/10 Pages) TELCOM

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TELCOM SEMICONDUCTOR, INC.

3-1/2 DIGIT A/D CONVERTERS

TC14433

TC14433A

PIN DESCRIPTIONS

Pin No.

24-Pin

28-Pin

PDIP/CerDip

SOIC

PLCC

Symbol

Description

VAG

This is the analog ground; it has a high input impedance — This pin

determines the reference level for the unknown input voltage (VX) and the

reference voltage (VREF).

VREF

Reference voltage — Full-scale output is equal to the voltage applied to

VREF. Therefore, full-scale voltage of 1.999V requires 2V reference and

199.9 mV full-scale requires a 200 mV reference. VREF functions as system

reset also. When switched to VEE, the system is reset to the beginning of

the conversion cycle.

The unknown input voltage (VX) is measured as a ratio of the reference

voltage (VREF) in a ratiometric A/D conversion.

These pins are for external components used for the integration function in

the dual slope conversion. Typical values are 0.1

µF (mylar) capacitor for C

R1/C1

R1 = 470 kW (resistor) for 2V full-scale.

R1 = 27 kW (resistor) for 200 mV full-scale. Clock frequency of 66 kHz gives

250 msec conversion time. See equation below for calculation of integrator

component values.

CO1

These pins are used for connecting the offset correction capacitor. The

CO2

recommended value is 0.1

µF.

Display update input pin — When DU is connected to the EOC output every

conversion is displayed. New data will be strobed into the output latches

during the conversion cycle if a positive edge is received on DU prior to the

ramp-down cycle. When this pin is driven from an external source, the

voltage should be referenced to VSS.

CLK1

Clock input pins — The TC14433 has its own oscillator system clock.

Connecting a single resistor between CLK1 and CLK0 sets the clock frequency.

CLK0

A crystal or OC circuit may be inserted in lieu of a resistor for improved

CLK1, the clock input, can be driven from an external clock source,

which need only have standard CMOS output drive. This pin is referenced to

VEE for external clock inputs. A 300 kW resistor yields a clock frequency of

about 66 kHz. (See typical characteristic curves; see Figure 9 for alternate

circuits.)

VEE

Negative power current — Connection pin for the most negative supply. Please

note the current for the output drive circuit is returned through VSS. Typical

supply current is 0.8 mA.

VSS

Negative power supply for output circuitry — This pin sets the low voltage level

for the output pins (BCD, Digit Selects, EOC, OR). When connected to analog

ground, the output voltage is from analog ground to VDD. If connected to VEE,

the output swing is from VEE to VDD. The recommended operating range for

VSS is between the VDD –3 volts and VEE.

EOC

End of conversion output generates a pulse at the end of each conversion

cycle. This generated pulse width is equal to one-half the period of the system

clock.

Overrange pin — Normally this pin is set high. When VX exceeds VREF the OR

pin is low.

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