4-221

TELCOM SEMICONDUCTOR, INC.

7

6

5

4

3

1

2

8

with 4.5V

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

Input

Logic 1 High Input Voltage

2.4

—

—

V

Logic 0 Low Input Voltage

—

—

0.8

V

Input Current

– 0V

IN

DD

– 10

—

10

µA

Output

High Output Voltage

—

—

V

Low Output Voltage

—

—

0.025

V

Output Resistance

—

9

12

Ω

Peak Output Current (Any Drain) Duty cycle <2%, t

≤ 300µsec

—

1.5

—

A

Continuous Output Current (Any Drain)

—

—

100

mA

Latch-Up Protection (Any Drain)

Duty cycle <2%, t

≤ 300µsec

>500

—

—

mA

Withstand Reverse Current

Switching Time (Note 1)

Rise Time

—

—

40

nsec

Fall Time

—

—

40

nsec

Delay Time

—

—

40

nsec

Delay Time

—

—

60

nsec

Power Supply

Power Supply Current

—

—

8

mA

—

—

0.6

NOTE

1. Switching times guaranteed by design.

PIN CONFIGURATIONS (DIP AND SOIC)

Circuit Layout Guidelines

Avoid long power supply and ground traces (added

inductance causes unwanted voltage transients). Use power

and ground planes wherever possible. In addition, it is

advisable that low ESR bypass capacitors (4.7

µF or 10µF

18

27

36

45

TC4405

B BOTTOM

COM

IN B

IN A

VDD

B TOP

A BOTTOM

A TOP

18

27

36

45

TC4405

B BOTTOM

COM

IN B

IN A

VDD

B TOP

A BOTTOM

A TOP

18

27

36

45

TC4404

B BOTTOM

COM

IN B

IN A

VDD

B TOP

A BOTTOM

A TOP

18

27

36

45

TC4404

B BOTTOM

COM

IN B

IN A

VDD

B TOP

A BOTTOM

A TOP

tantalum) be placed as close to the driver as possible. The

driver should be physically located as close to the device it

is driving as possible to minimize the length of the output

trace.

TC4404

TC4405

1.5A DUAL OPEN-DRAIN

MOSFET DRIVERS