LT3751EUFD datasheet(16/28 Pages) LINER

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LT3751

3751f

APPLICATIONS INFORMATION

The total propagation delay, td,isthesecondmostdominant

factor that affects efﬁciency and is the summation of gate

driver on-off propagation delays and the discharge time

associated with the secondary winding capacitance. There

are two effective methods to reduce the total propagation

delay. First, reduce the total capacitance on the secondary

winding, most notably the diode capacitance. Second,

reduce the total required NMOS gate charge. Figure 8

shows the effect of large secondary capacitance.

The energy stored in the secondary winding capacitance

is ½ • CSEC • VOUT2. This energy is reﬂected to the primary

when the diode stops forward conduction. If the reﬂected

capacitance is greater than the total NMOS drain capaci-

tance, the drain of the NMOS power switch goes negative

and its intrinsic body diode conducts. It takes some time

for this energy to be dissipated and thus adds to the total

propagation delay.

Choosing Regulator Maximum IPK

The IPK parameter in regulation mode is calculated based

on the desired maximum output power instead of charge

time like that in a capacitor charger application.

IPK = 2•

POUT(AVG)

Efficiency

•

VTRANS

VOUT

⎛

⎝⎜

⎞

⎠⎟

Note that the LT3751 regulation scheme varies the peak

current based on the output load current. The maximum

IPK is only reached during charge mode or during heavy

load conditions where output power is maximized.

Transformer Design

The transformer’s primary inductance, LPRI, is determined

by the desired VOUT and previously calculated N and IPK

parameters. Use the following equation to select LPRI:

LPRI =

μs• VOUT

IPK •N

The previous equation guarantees that the VOUTcomparator

has enough time to sense the ﬂyback waveform and trip

the DONE pin latch. Operating VOUT signiﬁcantly higher

then that used to calculate LPRI could result in a runaway

condition and overcharge the output capacitor.

The LPRI equation is adequate for most regulator applica-

tions. Note that if both IPK and N are increased signiﬁcantly

for a given VTRANS and VOUT, the maximum IPK will not be

reached within the refresh clock period. This will result in

a lower than expect maximum output power. To prevent

this from occurring, maintain the condition in the follow-

ing equation.

LPRI <

μs

IPK •

VTRANS

VOUT

⎡

⎣

⎢

⎤

⎦

⎥

The upper constraint on LPRI can be reduced by increas-

ing VTRANS and starting the design process over. The best

regulation occurs when operating the boundary-mode

frequency above 100kHz (refer to Operation section for

boundary-mode deﬁnition).

Figure 8. Effect of Secondary Winding Capacitance

VDRAIN

3751 F08

ISEC

IPRI

NO SEC.

CAPACITANCE

SEC. DISCHARGE

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