Interfaces

Pin Name

Type

Description

Global Signals

clk

in

System clock

reset_n

in

Asynchronous system

reset, active low

VME Bus

vme_addr_in[31:1]

in

Address bus input

vme_addr_out[31:1]

out

Address bus output

vme_addr_int_drv_n

out

Internal i/o driver enable

vme_addr_drv_n

out

External address bus

driver enable

vme_addr_dir

out

External address bus

driver direction

vme_am[5:0]

in

Address modifier code

vme_data_in[31:0]

in

Data bus input

vme_data_out [31:0]

out

Data bus output

vme_data_int_drv_n

out

Internal i/o driver enable

vme_data_drv_n

out

External data bus driver

enable

vme_data_dir

out

External data bus driver

direction

vme_ds0_n

in

Data strobe 0

vme_ds1_n

in

Data strobe 1

vme_lword_in_n

in

Long word indicator, in

vme_lword_out_n

out

Long word indicator, out

vme_as_n

in

Address strobe

vme_write_n

in

Read write not indicator

vme_dtack_n

out

Data acknowledge

vme_berr_n

in

Bus error

vme_iack_n

in

Interrupt acknowledge

Pin Name

Type

Description

vme_iack_in_n

in

Interrupt acknowledge

chain in

vme_iack_out_n

out

Interrupt acknowledge

chain out

vme_irq_n[6:0]

out

Interrupt request

User Side Bus

user_addr[31:2]

out

Address bus

user_am[5:0]

out

Address modifier code

user_acc_req

out

Data access request

user_acc_rdy

in

Data access request

ready

user_data_rd[31:0]

in

Data read bus

user_data_wr[31:0]

out

Data write bus

user_rwn

out

Data read or write

access

user_byte_valid

[3:0]

out

Data byte valid

User Decode

int_user_addr[31:1]

out

Address bus

int_user_am[5:0]

out

Address modifier code

user_access_ebl

in

Valid user access

user_access_ebl_

mblt

in

Valid user access mblt

mode

Interrupt

user_iack

out

Interrupt acknowledge

user_ireq

in

Interrupt request

user_ivec[31:0]

in

Interrupt vector

user_ilevel[2:0]

in

Interrupt request level

INICORE INC. 5600 Mowry School Road Suite 180 Newark, CA 94560 Tel: 510 445 1529 Fax: 510 656 0995 www.inicore.com

About Inicore

 FPGA and ASIC Design

 Easy-to-use IP Cores

 System-on-Chip Solutions

 Consulting Services

 ASIC to FPGA Migration

 Obsolete ASIC Replacements

Inicore is an experienced

system design house providing

FPGA / ASIC and SoC design

services. The company's

expertise in architecture,

intellectual property,

methodology and tool handling

provides a complete design

environment that helps

customers shorten their design

cycle and speed time to market.

Our offering covers feasibility

study, concept analysis,

architecture definition, code

generation and implementation.

When ready, we deliver you a

FPGA or take your design to an

ASIC provider, whatever is

more suitable for your unique

solution.

Deliverables

The core is available as Actel

optimized netlist or as RTL

version.

Actel Optimized Netlist:

• Netlist for target FPGA, EDIF,

Verilog and VHDL format

• User Guide

RTL Source Code:

• VHDL or Verilog source code

• Funtional verification

testbench

• Synthesis script

• Timing constraints

• User guide

Page 2/2

Figure 2: Symbol

© 2003, Inicore Inc, All rights reserved.

All brands or product names mentioned are

the property of their respective holders.

51415.71.02 Sept/2003

V M E S la v e

r e s e t _ n

c l k _ s y s

v m e _ a m [ 5 :0 ]

v m e _ d a t a _ i n [ 3 1 : 0 ]

v m e _ d a t a _ d r v _ n

v m e _ d a t a _ d ir

v m e _ d s 0 _ n

v m e _ d s 1 _ n

v m e _ lw o r d _ i n _ n

v m e _ a s _ n

v m e _ w r it e _ n

v m e _ d t a c k _ n

v m e _ b e r r _ n

v m e _ ia c k _ n

v m e _ ia c k _ i n _ n

v m e _ ia c k _ o u t _ n

v m e _ ir q _ n [ 6 :0 ]

v m e _ d a t a _ o u t [ 3 1 : 0 ]

v m e _ d a t a _ i n t _ d r v _ n

in t _ u s e r _ a m [ 5 :0 ]

in t _ u s e r _ a d d r [ 3 1 : 1 ]

u s e r _ a c c e s s _ e b l

u s e r _ ia c k

u s e r _ ir e q

u s e r _ il e v [ 2 : 0 ]

u s e r _ iv e c [ 3 1 :0 ]

u s e r _ a d d r [ 3 1 :2 ]

u s e r _ a m [ 5 :0 ]

u s e r _ a c c _ r e q

u s e r _ a c c _ r d y

u s e r _ d a t a _ r d [ 3 1 : 0 ]

u s e r _ d a t a _ w r [ 3 1 : 0 ]

u s e r _ r w n

u s e r _ b y t e _ v a li d [ 3 : 0 ]

u s e r _ a c c e s s _ e b l _ m b lt

v m e _ a d d r _ i n [ 3 1 : 1 ]

v m e _ lw o r d _ o u t _ n

v m e _ a d d r _ d r v _ n

v m e _ a d d r _ d ir

v m e _ a d d r _ o u t [ 3 1 : 1 ]

v m e _ a d d r _ i n t _ d r v _ n