Copyright © by Eureka Technology Inc.

4962 El Camino Real,

Los Altos, CA 94022, USA

Tel: 1 650 960 3800

Fax: 1 650 960 3805

http://www.eurekatech.com

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Eureka Technology

Description

The EP501 NAND Flash controller provides an easy interface for user to access

NAND Flash devices. Typical NAND Flash devices are accessed through compli-

cated sequence of command, address, data, and confirmation protocols. The

EP501 manages all the hardware protocols and allows the user to access NAND

Flash memory simply by reading and writing control registers inside the EP501.

A very large size of NAND Flash memory can be accessed through a small num-

ber of control registers. The NAND Flash controller occupies only a small size in

the system’s memory space without scarifying system performance. Burst access

to the NAND Flash memory is supported by the controller at full memory band-

width. Timing parameters of the controller is fully programmable so different

memory speeds are supported regardless of the operating frequency of the control-

ler.

The EP501 supports optional error correction code (ECC) that performs single-bit

error correction and double-bit error detection. There are options to provide ECC

protection on per word basis or per page basis. With per word ECC, 8 bits of ECC

code is generated by the core for each 32-bit data. A total for 40 bit is written to

the NAND Flash for each data word. Error detection and correction are automati-

cally performed by the core with error logging through internal control registers.

The core can be configure to generate interrupt on ECC error. ECC error can also

be injected into the NAND Flash device if desired for diagnostic purpose. With

per page ECC, 3 bytes of ECC code is generated for every page (512 bytes) of

data.

The EP501 is programmable to support both large block and small block NAND

Flash devices. Memory size, bus width, access timing, and number of banks are

all programmable.

Several options of user interface are available for the user to choose from. The

standard version features a simple user interface that is designed for on-chip sys-

tem integration. It has separate address and data buses and command signals that

supports burst transfer and wait state insertion. Other standard interface buses

including PCI, AMBA AHB, PCMCIA, and CardBus are available. The controller

acts as a target or slave device on these buses. With these standard bus interfaces,

the EP501 can be integrate seamlessly with systems built on these standards.

Optional Features

The EP501 NAND Flash controller supports the following optional features per

customer specification

Error Correction Code (ECC)

Power-on boot ROM support.

EP501 NAND Flash

Controller