LTC4309

4

4309fa

TIMING DIAGRAMS

ENABLE and READY Timing

ENABLE

CONNECT

READY

4309 TD01

SDA/SCL Propagation Delays, Rise and Fall Times

SDAIN/SCLIN

SDAOUT/SCLOUT

4309 TD02

Figure 1. Timing Diagrams

SYMBOL

PARAMETER

CONDITIONS

MIN TYP MAX UNITS

SDA, SCL Logic Input Threshold Voltage

Hysteresis

(Note 3)

50

mV

Digital Input Capacitance SDAIN,

SDAOUT, SCLIN, SCLOUT

(Note 3)

10

pF

Input Leakage Current

SDA, SCL, ACC, DISCEN Pins

l

±5

μA

Output Low Voltage

l

0

0.4

V

mV

Buffer Input Logic Low Voltage

l

1.2

V

Bus Stuck Low Timeout

Bus Stuck Low Timer

SDAOUT, SCLOUT = OV

l

25

30

35

ms

FAULT Output Low Voltage

l

0.4

V

FAULT Off Leakage Current

l

0.1

±5

μA

The

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Test performed with connection circuity active.

Note 3: Determined by design, not subject to test.

Note 4: For larger equivalent bus capacitance, the skew increases, and

setup and hold times must be adjusted accordingly. Please see the

Operation Section of the datasheet.

Note 6: All currents into pins are positive, all voltages are referenced to

GND, unless otherwise specified.

Typical Performance Characteristics section.

ELECTRICAL CHARACTERISTICS