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LTC6912IGN-2 Datasheet(PDF) 11 Page - Linear Technology |
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LTC6912IGN-2 Datasheet(HTML) 11 Page - Linear Technology |
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11 / 24 page  LTC6912 11 6912fa ELECTRICAL CHARACTERISTICS The ● denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted. SERIAL I TERFACE SPECIFICATIO S C, I GRADES H GRADE PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Specifications for the LTC6912-2 ONLY Voltage Noise Density f = 50kHz (Referred to Input) Gain = 1 31.1 31.1 nV/ √Hz Gain = 2 22.8 22.8 nV/ √Hz Gain = 4 17 17 nV/ √Hz Gain = 8 14.6 14.6 nV/ √Hz Gain = 16 13.2 13.2 nV/ √Hz Gain = 32 12.9 12.9 nV/ √Hz Gain = 64 12.6 12.6 nV/ √Hz Total Harmonic Distortion Gain = 8, fIN = 10kHz, VOUT = 1VRMS –84 –84 dB 0.006 0.006 % Gain = 8, fIN = 100kHz, VOUT = 1VRMS –82 –82 dB 0.008 0.008 % SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital I/O Logic Levels, All Digital I/O Voltage Referenced to DGND VIH Digital Input High Voltage ● 2V VIL Digital Input Low Voltage ● 0.8 V VOH Digital Output High Voltage Sourcing 500 µA ● V+ – 0.3 V VOL Digital Output Low Voltage Sinking 500 µA ● 0.3 V Serial Interface Timing, V+ = 2.7V ~ 4.5V, V– = 0V (Note 10) t1 DIN Valid to CLK Setup ● 60 ns t2 DIN Valid to CLK Hold ● 0ns t3 CLK Low ● 100 ns t4 CLK High ● 100 ns t5 CS/LD Pulse Width ● 60 ns t6 LSB CLK to CS/LD ● 60 ns t7 CS/LD Low to CLK ● 30 ns t8 DOUT Output Delay CL = 15pF ● 125 ns t9 CLK Low to CS/LD Low ● 0ns Serial Interface Timing, V+ = 4.5V ~ 5.5V, V– = 0V (Note 10) t1 DIN Valid to CLK Setup ● 30 ns t2 DIN Valid to CLK Hold ● 0ns t3 CLK Low ● 50 ns t4 CLK High ● 50 ns t5 CS/LD Pulse Width ● 40 ns t6 LSB CLK to CS/LD ● 40 ns t7 CS/LD Low to CLK ● 20 ns t8 DOUT Output Delay CL = 15pF ● 85 ns t9 CLK Low to CS/LD Low ● 0ns |
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