LTC2245 datasheet(13/20 Pages) LINER

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LTC2245

2245fa

APPLICATIO S I FOR ATIO

The noise performance of the LTC2245 can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2245 is 10Msps.

For the ADC to operate properly, the CLK signal should

have a 50% (

±10%) duty cycle. Each half cycle must have

at least 40ns for the ADC internal circuitry to have enough

settling time for proper operation.

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The input

clock duty cycle can vary and the clock duty cycle stabilizer

will maintain a constant 50% internal duty cycle. If the

clock is turned off for a long period of time, the duty cycle

stabilizer circuit will require a hundred clock cycles for the

PLL to lock onto the input clock. To use the clock duty

cycle stabilizer, the MODE pin should be connected to

1/3VDD or 2/3VDD using external resistors.

The lower limit of the LTC2245 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC2245 is 1Msps.

The difference amplifier generates the high and low refer-

ence for the ADC. High speed switching circuits are

connected to these outputs and they must be externally

bypassed. Each output has two pins. The multiple output

pins are needed to reduce package inductance. Bypass

capacitors must be connected as shown in Figure 6.

Other voltage ranges in-between the pin selectable ranges

can be programmed with two external resistors as shown

in Figure 7. An external reference can be used by applying

its output directly or through a resistor divider to SENSE.

It is not recommended to drive the SENSE pin with a logic

device. The SENSE pin should be tied to the appropriate

level as close to the converter as possible. If the SENSE pin

is driven externally, it should be bypassed to ground as

close to the device as possible with a 1

µF ceramic capacitor.

Input Range

The input range can be set based on the application. The

2V input range will provide the best signal-to-noise perfor-

mance while maintaining excellent SFDR. The 1V input

range will have better SFDR performance, but the SNR will

degrade by 5.8dB.

Driving the Clock Input

The CLK input can be driven directly with a CMOS or TTL

level signal. A differential clock can also be used along with

a low-jitter CMOS converter before the CLK pin (see

Figure 8).

Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter

CLK

100

Ω

0.1

µF

4.7

µF

FERRITE

BEAD

CLEAN

SUPPLY

IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

2245 F08

LTC2245

Figure 7. 1.5V Range ADC

VCM

SENSE

1.5V

0.75V

2.2

µF

12k

µF

12k

2245 F07

LTC2245

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