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LTC2245

2245fa

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overflow bit.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2245 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Data Format

Using the MODE pin, the LTC2245 parallel digital output

can be selected for offset binary or 2’s complement

format. Connecting MODE to GND or 1/3VDD selects offset

binary output format. Connecting MODE to

2/3VDD or VDD selects 2’s complement output format.

An external resistor divider can be used to set the 1/3VDD

or 2/3VDD logic values. Table 2 shows the logic states for

the MODE pin.

APPLICATIO S I FOR ATIO

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50

Ω to external

circuitry and may eliminate the need for external damping

resistors.

Table 1. Output Codes vs Input Voltage

AIN+ – AIN–

D13 – D0

(2V Range)

(Offset Binary)

(2’s Complement)

>+1.000000V

11 1111 1111 1111

01 1111 1111 1111

+0.999878V

11 1111 1111 1111

01 1111 1111 1111

+0.999756V

11 1111 1111 1110

01 1111 1111 1110

+0.000122V

10 0000 0000 0001

00 0000 0000 0001

0.000000V

10 0000 0000 0000

00 0000 0000 0000

–0.000122V

01 1111 1111 1111

11 1111 1111 1111

–0.000244V

01 1111 1111 1110

11 1111 1111 1110

–0.999878V

00 0000 0000 0001

10 0000 0000 0001

–1.000000V

00 0000 0000 0000

10 0000 0000 0000

<–1.000000V

00 0000 0000 0000

10 0000 0000 0000

LTC2245

2245 F09

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 9. Digital Output Buffer

Table 2. MODE Pin Function

Clock Duty

MODE Pin

Output Format

Cycle Stablizer

Offset Binary

Off

1/3VDD

Offset Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

Overflow Bit

When OF outputs a logic high the converter is either

overranged or underranged.

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