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LTC2251/LTC2250

22510fa

APPLICATIO S I FOR ATIO

to the same power supply as for the logic being driven. For

example if the converter is driving a DSP powered by a 1.8V

supply, then OVDD should be tied to that same 1.8V supply.

OVDD can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND up

to 1V and must be less than OVDD. The logic outputs will

swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin, OE.

OE high disables all data outputs including OF. The data ac-

cess and bus relinquish times are too slow to allow the

outputs to be enabled and disabled during full speed op-

eration. The output Hi-Z state is intended for use during long

periods of inactivity.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normal operation. Connecting SHDN to VDD and OE to VDD

results in sleep mode, which powers down all circuitry

including the reference and typically dissipates 1mW. When

exiting sleep mode it will take milliseconds for the output

data to become valid because the reference capacitors have

to recharge and stabilize. Connecting SHDN to VDD and OE

to GND results in nap mode, which typically dissipates

15mW. In nap mode, the on-chip reference circuit is kept

on, so that recovery from nap mode is faster than that from

sleep mode, typically taking 100 clock cycles. In both sleep

and nap modes, all digital outputs are disabled and enter

the Hi-Z state.

Grounding and Bypassing

The LTC2251/LTC2250 requires a printed circuit board

with a clean, unbroken ground plane. A multilayer board

with an internal ground plane is recommended. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-

tors must be located as close to the pins as possible. Of

For full speed operation the capacitive load should be kept

under 10pF.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Data Format

Using the MODE pin, the LTC2251/LTC2250 parallel

digital output can be selected for offset binary or 2’s

complement format. Connecting MODE to GND or

1/3VDD selects offset binary output format. Connecting

MODE to 2/3VDD or VDD selects 2’s complement output

format. An external resistor divider can be used to set the

1/3VDD or 2/3VDD logic values. Table 2 shows the logic

states for the MODE pin.

Table 2. MODE Pin Function

Clock Duty

MODE Pin

Output Format

Cycle Stablizer

Offset Binary

Off

1/3VDD

Offset Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

Figure 14. Digital Output Buffer

22510 F14

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V

TO VDD

PREDRIVER

LOGIC

DATA

FROM

LATCH

LTC2251/LTC2250

Overflow Bit

When OF outputs a logic high the converter is either

overranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

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