LTC2280 datasheet(18/24 Pages) LINER

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LTC2280

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APPLICATIO S I FOR ATIO

Overflow Bit

When OF outputs a logic high the converter is either

overranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

example, if the converter is driving a DSP powered by a 1.8V

supply, then OVDD should be tied to that same 1.8V supply.

OVDD can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND up

to 1V and must be less than OVDD. The logic outputs will

swing between OGND and OVDD.

Output Enable

The outputs may be disabled with the output enable pin, OE.

OE high disables all data outputs including OF. The data ac-

cess and bus relinquish times are too slow to allow the

outputs to be enabled and disabled during full speed op-

eration. The output Hi-Z state is intended for use during long

periods of inactivity. Channels A and B have independent

output enable pins (OEA, OEB).

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normal operation. Connecting SHDN to VDD and OE to VDD

results in sleep mode, which powers down all circuitry

including the reference and typically dissipates 1mW. When

exiting sleep mode it will take milliseconds for the output

data to become valid because the reference capacitors have

Table 2. MODE Pin Function

Clock Duty

MODE Pin

Output Format

Cycle Stabilizer

Offset Binary

Off

1/3VDD

Offset Binary

2/3VDD

2’s Complement

VDD

2’s Complement

Off

to recharge and stabilize. Connecting SHDN to VDD and OE

to GND results in nap mode, which typically dissipates

30mW. In nap mode, the on-chip reference circuit is kept

on, so that recovery from nap mode is faster than that from

sleep mode, typically taking 100 clock cycles. In both sleep

and nap modes, all digital outputs are disabled and enter

the Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA,

SHDNB). Channel A is controlled by SHDNA and OEA, and

Channel B is controlled by SHDNB and OEB. The nap, sleep

and output enable modes of the two channels are completely

independent, so it is possible to have one channel operat-

ing while the other channel is in nap or sleep mode.

Digital Output Multiplexer

The digital outputs of the LTC2280 can be multiplexed onto

a single data bus if the sample rate is 80Msps or less. The

MUX pin is a digital input that swaps the two data busses.

If MUX is High, Channel A comes out on DA0-DA9, OFA;

Channel B comes out on DB0-DB9, OFB. If MUX is Low, the

output busses are swapped and Channel A comes out on

DB0-DB9, OFB; Channel B comes out on DA0-DA9, OFA.

To multiplex both channels onto a single output bus, con-

nect MUX, CLKA and CLKB together (see the Timing Dia-

gram for the multiplexed mode). The multiplexed data is

available on either data bus—the unused data bus can be

disabled with its OE pin.

Grounding and Bypassing

The LTC2280 requires a printed circuit board with a clean,

unbroken ground plane. A multilayer board with an inter-

nal ground plane is recommended. Layout for the printed

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-

tors must be located as close to the pins as possible. Of

particular importance is the 0.1

µF capacitor between

REFH and REFL. This capacitor should be placed as close

to the device as possible (1.5mm or less). A size 0402

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