LTC2494 datasheet(21/36 Pages) LINER

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LTC2494

2494fb

Figure 4. Internal PTAT Digital Output vs Temperature

Figure 5. Absolute Temperature Error

Table 6. LTC2494 Interface Timing Modes

CONFIGURATION

SCK

SOURCE

CONVERSION

CYCLE CONTROL

DATA OUTPUT

CONTROL

CONNECTION AND

WAVEFORMS

External SCK, Single Cycle

Conversion

External

CS and SCK

Figures 6, 7

External SCK, 3-Wire I/O

External

SCK

Figure 8

Internal SCK, Single Cycle

Conversion

Internal

CS↓

Figures 9, 10

Internal SCK, 3-Wire I/O,

Continuous Conversion

Internal

Continuous

Internal

Figure 11

External Serial Clock, Single Cycle Operation

This timing mode uses an external serial clock to shift out

the conversion result and CS to monitor and control the

state of the conversion cycle (see Figure 6).

The external serial clock mode is selected during the power-

up sequence and on each falling edge of CS. In order to

enter and remain in the external SCK mode of operation,

SCK must be driven LOW both at power up and on each

CS falling edge. If SCK is HIGH on the falling edge of CS,

the device will switch to the internal SCK mode.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the conversion is complete and the device is in the sleep

state. Independent of CS, the device automatically enters

the sleep state once the conversion is complete; however,

in order to reduce the power, CS must be HIGH.

When the device is in the sleep state, its conversion result

is held in an internal static shift register. The device remains

in the sleep state until the ﬁrst rising edge of SCK is seen

while CS is LOW. The input data is then shifted in via the

SDI pin on each rising edge of SCK (including the ﬁrst rising

edge). The channel selection and converter conﬁguration

mode will be used for the following conversion cycle. If

the input channel or converter conﬁguration is changed

during this I/O cycle, the new settings take effect on the

conversion cycle following the data input/output cycle.

The output data is shifted out the SDO pin on each falling

edge of SCK. This enables external circuitry to latch the

output on the rising edge of SCK. EOC can be latched on

the ﬁrst rising edge of SCK and the last bit of the conver-

sion result can be latched on the 24th rising edge of SCK.

On the 24th falling edge of SCK, the device begins a new

conversion and SDO goes HIGH (EOC = 1) indicating a

conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

APPLICATIONS INFORMATION

TEMPERATURE (K)

480

640

800

960

1020

400

2494 F04

320

300

200

100

160

VCC = 5V

VREF = 5V

SLOPE = 2.45 LSB16/K

TEMPERATURE (

°C)

–55

–30

–5

–4

–3

–2

–1

120

2494 F05

–5

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