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AWT6321 Datasheet(PDF) 6 Page - ANADIGICS, Inc |
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AWT6321 Datasheet(HTML) 6 Page - ANADIGICS, Inc |
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6 / 8 page ![]() 6 Data Sheet - Rev 2.2 10/2008 AWT6321 APPLICATION INFORMATION To ensure proper performance, refer to all related Application Notes on the ANADIGICS web site: http://www.anadigics.com Shutdown Mode The power amplifier may be placed in a shutdown mode by applying logic low levels (see Operating Ranges table) to the VENABLE and VMODE voltages. Table 6: Bias Control Bias Modes The power amplifier may be placed in either a Low Bias mode or a High Bias mode by applying the appropriate logic level (see Operating Ranges table) to the VMODE voltages. The Bias Control table lists the recommended modes of operation for various applications. Figure 3: Application Circuit Bias Control RFIN_CELL 1 13 11 14 12 3 4 2 GND 5 6 10 9 Bias Control GND RFIN_PCS GND at slug (pad) GND VMODE VBATT VEN_CELL VEN_PCS VCC 68 pF 1000 pF 0.01 F 10 F 2.2 F 0.01 F Note: (1) Add blocking cap if DC voltage is present on input pin. (2) TRL should be short and of 50 characteristic impedance. (3) TRL 5 should be as long as possible (minimum of 0.1 at 800 MHz) and capable of handling 1200 mA current. 8 7 GND (1) (1) N/C RFOUT_CELL TRL5 TRL3 TRL1 TRL2 15 pF RFOUT_PCS TRL4 (2) (2) (2) (2) (3) APPLICATION POUT LEVELS BIAS MODE VENABLE VMODE VCC VBATT CDMA - low power < +16 dBm Low +2.4 V +2.4 V 3.2 - 4.2 V > 3.2 V CDMA - high power > +16 dBm High +2.4 V 0 V 3.2 - 4.2 V > 3.2 V Optional lower VCC in low power mode < +7 dBm Low +2.4 V +2.4 V 1.5 V > 3.2 V Shutdown - Shutdown 0 V 0 V 3.2 - 4.2 V > 3.2 V |
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