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LTC2928

2928f

Using an Enable Line to Generate a Sequencing-Up

Delay

APPLICATIO S I FOR ATIO

Anotherinterestingapplicationcombinestheusageofboth

the CAS pin connection and the DONE—ON communica-

tions link. Figure 4 shows a two dimensional conﬁgura-

tion of four LTC2928s that allows for 16 supplies to be

sequenced in up to 16 time positions.

CAS

DONE

STMR

LTC2928

(MASTER/FIRST)

16 SUPPLIES, 16 TIME POSITIONS

VCC

DONE

STMR

LTC2928

(MASTER/NOT FIRST)

(SLAVE/FIRST)

CAS

VCC

DONE

LTC2928

VCC

DONE

LTC2928

2928 F04

CAS

Figure 4. Two-dimensional application.

In this application, both slave devices are clocked by the

masters through their CAS pins. Again, sequencing-up

begins with ON pulling high. Although the ON input is high

on the device in the lower right quadrant, sequencing-up

will not begin there until the ﬁrst master (upper left), and

its slave are ﬁnished sequencing-up. At that time the



DONE pin will pull up the ON pin of the second master.

The second master and slave will then start sequencing

up their supplies.

VCC

RT2

IEN (10uA)

CDEL

EN2

LTC2928

2928 F05

Figure 5. Adjustable Sequencing Delay

An arbitrary delay between enables may be added by

using an enable pull-up current (10μA) to charge a delay

capacitor (Figure 5). Position the delay using an RT resis-

tor. Assuming 100% sequencing thresholds (0.5V) and

a fully discharged delay capacitor (CDEL), the added time

delay (TDEL) is:

DEL

( )

= •

Be sure to account for the extra delay when using the

power-good timer (PTMR).

Extending Sequencing Delay to Subsequent Supplies

Sequencing delays can be extended after certain events by

paralleling capacitance to the STMR pin. Figure 6 shows

one way to add capacitance after a particular enable output

pulls high.

RESISTOR LIMITS

GATE VOLTAGE

CSTMR

EN2

STMR

VCC

LTC2928

CADD

2928 F06

Figure 6. Adding STMR capacitance

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