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LTC3872 Datasheet(PDF) 14 Page - Linear Technology |
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LTC3872 Datasheet(HTML) 14 Page - Linear Technology |
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14 / 20 page ![]() LTC3872 14 3872fa APPLICATIO S I FOR ATIO 3. Assuming a MOSFET junction temperature of 125°C, the room temperature MOSFET RDS(ON) should be less than: RV D I DS ON SENSE MAX MAX OMAX () ( ) ( • – • ≤ + ⎛ ⎝⎜ ⎞ ⎠⎟ 1 1 2 χ )) • .• –. . •• . ρT V A m = + ⎛ ⎝⎜ ⎞ ⎠⎟ ≈Ω 0 175 10 39 1 04 2 21 5 30 The MOSFET used was the Si3460, which has a maximum RDS(ON) of 27mΩ at 4.5V VGS, a BVDSS of greater than 30V, and a gate charge of 13.5nC at 4.5V VGS. 4. The diode for this design must handle a maximum DC output current of 2A and be rated for a minimum reverse voltage of VOUT, or 5V. A 25A, 15V diode from On Semi- conductor (MBRB2515L) was chosen for its high power dissipation capability. 5. The output capacitor usually consists of a lower valued, low ESR ceramic. 6. The choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design two 22μF Taiyo Yuden ceramic capacitors (JMK325BJ226MM) is required (the input and return lead lengths are kept to a few inches. As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3872. These items are illustrated graphically in the layout diagram in Figure 7. Check the following in your layout: 1. The Schottky diode should be closely connected be- tween the output capacitor and the drain of the external MOSFET. 2. The input decoupling capacitor (0.1μF) should be con- nected closely between VIN and GND. 3. The trace from SW to the switch point should be kept short. 4. Keep the switching node NGATE away from sensitive small signal nodes. 5. The VFB pin should connect directly to the feedback resistors. The resistive divider R1 and R2 must be con- nected between the (+) plate of COUT and signal ground. Figure 7. LTC3872 Layout Diagram (See PC Board Layout Checklist) IPRG ITH VFB GND SW RUN/SS VIN NGATE LTC3872 3872 F07 R1 R2 RITH CIN COUT VOUT VIN CITH D1 M1 L1 BOLD LINES INDICATE HIGH CURRENT PATHS |
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