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LTC4097

4097f

APPLICATIONS INFORMATION

the nearest 1% value is 105k.

R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k

the nearest 1% value is 12.7k. The ﬁnal solution is shown

in Figure 5 and results in an upper trip point of 45°C and

a lower trip point of 0°C.

Protecting the USB Pin and Wall Adapter Input from

Overvoltage Transients

Caution must be exercised when using ceramic capaci-

tors to bypass the USBIN or the wall adapter inputs. High

voltage transients can be generated when the USB or wall

adapter is hot plugged. When power is supplied via the

USB bus or wall adapter, the cable inductance along with

the self resonant and high Q characteristics of ceramic

capacitors can cause substantial ringing which could

exceed the maximum voltage ratings and damage the

LTC4097. Refer to Linear Technology Application Note 88,

entitled “Ceramic Input Capacitors Can Cause Overvoltage

Transients” for a detailed discussion of this problem.

Always use an oscilloscope to check the voltage wave-

forms at the USBIN and DCIN pins during USB and wall

adapter hot-plug events to ensure that overvoltage

transients have been adequately removed.

Reverse Polarity Input Voltage Protection

In some applications, protection from reverse polarity

voltage on the input supply pins is desired. If the sup-

ply voltage is high enough, a series blocking diode can

be used. In other cases where the voltage drop must be

kept low, a P-channel MOSFET can be used (as shown in

Figure 6).

WALL

ADAPTER

DCIN

LTC4097

DRAIN-BULK

DIODE OF FET

4097 F06

Figure 6. Low Loss Input Reverse Polarity Protection

LTC4097 Datasheet(PDF) 18 Page - Linear Technology