BQ4287 datasheet(3/8 Pages) TI

3 / 8 page

Nov. 1993 C

Power-Down/Power-Up Timing (T

A =TOPR)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

Conditions

VCC slew from 4.5V to 0V

300

µs

VCC slew from 0V to 4.5V

100

µs

tCSR

CS at VIH after power-up

200

Internal write-protection

period after VCC passes VPFD

on power-up.

tDR

Data-retention and time-

keeping time

years

TA = 25°C, no load on VOUT or

CEOUT.

tWPT

Write-protect time for

external RAM

µs

Delay after VCC slows down

past VPFD before SRAM is

write-protected.

tCER

Chip enable recovery time

tCSR

-tCSR

Time during which external

SRAM is write-protected after

VCC passes VPFD on power-up.

tCED

Chip enable propagation

delay to external SRAM

Note:

Clock accuracy is better than

± 1 minute per month at 25°C for the period of tDR.

Caution:

Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Power-Down/Power-Up Timing

bq4287

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