6

Hold Time, SPE to CP

-

4.5

3

-

-

3

-

3

-

ns

Recovery Time, MR to CP (161)

-

4.5

15

-

-

19

-

22

-

ns

NOTE:

7. Applies to non-cascaded operation only. With cascaded counters clock to terminal count propagation delays, count enables (PE or TE)-

to-clock setup times, and count enables (PE or TE)-to-clock hold times determine maximum clock frequency. For example with these HC

devices:

Prerequisite For Switching Specifications

(Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

(V)

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

f

1

CP-to-TC prop. delay

TE-to-CP setup

TE-to-CP Hold

++

-----------------------------------------------------------------------------------------------------------------------------------------------------

1

37

10

0

++

-----------------------------

21MHz min

()

≈

==

PARAMETER

SYMBOL

TEST

CONDITIONS

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

HC TYPES

Propagation Delay

CP to TC

2

-

-

185

-

230

-

280

ns

4.5

-

-

37

-

46

-

56

ns

5

-

15

-

-

-

-

-

ns

6

-

-

31

-

39

-

48

ns

CP to Qn

2

-

-

185

-

230

-

280

ns

4.5

-

-

37

-

46

-

56

ns

5

-

15

-

-

-

-

-

ns

6

-

-

31

-

39

-

48

ns

TE to TC

2

-

-

120

-

150

-

180

ns

4.5

-

-

24

-

30

-

36

ns

5

-

9

-

-

-

-

-

ns

6

-

-

20

-

26

-

31

ns

MR to Qn (161)

2

-

-

210

-

265

-

315

ns

4.5

-

-

42

-

53

-

63

ns

5

-

18

-

-

-

-

-

ns

6

-

-

36

-

45

-

54

ns

MR to TC (161)

2

-

-

210

-

265

-

315

ns

4.5

-

-

42

-

53

-

63

ns

6

-

-

36

-

45

-

54

ns

Output Transition Time

2

-

-

75

-

95

-

110

ns

4.5

-

-

15

-

19

-

22

ns

6

-

-

13

-

16

-

19

ns

Power Dissipation Capacitance

(Notes 8, 9)

-5

-

60

-

-

-

-

-

pF

CD74HC161, CD74HCT161, CD74HC163, CD74HCT163