1

Data sheet acquired from Harris Semiconductor

SCHS163

Features

• Synchronous Counting and Asynchronous

Loading

• Two Outputs for N-Bit Cascading

• Look-Ahead Carry for High-Speed Counting

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Pinout

CD74HC192, CD74HC193, CD74HCT193

(PDIP, SOIC)

TOP VIEW

Description

The Harris CD74HC192, CD74HC193 and CD74HCT193 are

asynchronously

presettable

BCD

Decade

and

Binary

Up/Down synchronous counters, respectively.

Presetting the counter to the number on the preset data inputs

(P0-P3) is accomplished by a LOW asynchronous parallel

load input (PL). The counter is incremented on the low-to-high

transition of the Clock-Up input (and a high level on the Clock-

Down input) and decremented on the low to high transition of

the Clock-Down input (and a high level on the Clock-up input).

A high level on the MR input overrides any other input to clear

the counter to its zero state. The Terminal Count up (carry)

goes low half a clock period before the zero count is reached

and returns to a high level at the zero count. The Terminal

Count Down (borrow) in the count down mode likewise goes

low half a clock period before the maximum count (9 in the

192 and 15 in the 193) and returns to high at the maximum

count. Cascading is effected by connecting the carry and

borrow outputs of a less significant counter to the Clock-Up

and CLock-Down inputs, respectively, of the next most

significant counter.

If a decade counter is present to an illegal state or assumes

an illegal state when power is applied, it will return to the

normal sequence in one count as shown in state diagram.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

P1

Q1

Q0

CPD

CPU

Q2

GND

Q3

MR

TCD

TCU

PL

P2

P3

P0

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG.

NO.

CD74HC192E

-55 to 125

16 Ld PDIP

E16.3

CD74HC193E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT193E

-55 to 125

16 Ld PDIP

E16.3

CD74HCT193M

-55 to 125

16 Ld SOIC

M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer or die for this part number is available which meets all elec-

trical specifications. Please contact your local sales office or

Harris customer service for ordering information.

September 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1674.1

CD74HC192, CD74HC193,

CD74HCT193

High Speed CMOS Logic

Presettable Synchronous 4-Bit Up/Down Counters

[ /Title

(CD74

HC192

,

CD74

HC193

,

CD74

HCT19

3)

/Sub-

ject

(High

Speed

CMOS

Logic

Preset-