9

FIGURE 2. CD74HC193 SYNCHRONOUS BINARY COUNTERS, TYPICAL RESET, PRESET AND COUNT SEQUENCES

FIGURE 3. CLOCK TO OUTPUT DELAYS AND CLOCK PULSE

WIDTH

FIGURE 4. CLOCK TO TERMINAL COUNT DELAYS

FIGURE 5. PARALLEL LOAD PULSE WIDTH, PARALLEL

LOAD TO OUTPUT DELAYS, AND PARALLEL

LOAD TO CLOCK RECOVERY TIME

FIGURE 6. MASTER RESET PULSE WIDTH, MASTER RESET

TO OUTPUT DELAY AND MASTER RESET TO

CLOCK RECOVERY TIME

MASTER RESET

ASYNCHRONOUS PARALLEL LOAD

PRESET DATA

P0

P1

P2

P3

CLOCK UP

CLOCK DOWN

OUTPUTS

TERMINAL COUNT UP

TERMINAL COUNT DOWN

013

14

15

0

1

2

COUNT DOWN

COUNT UP

RESET

1

0

15

14

13

PRESET

SEQUENCES:

1. RESET OUTPUTS TO ZERO.

2. LOAD (PRESET) TO BINARY THIRTEEN.

3. COUNT UP TO FOURTEEN,

FIFTEEN, TERMINAL COUNT UP,

ZERO, ONE AND TWO.

4. COUNT DOWN TO ONE, ZERO,

TERMINAL COUNT DOWN,

FIFTEEN, FOURTEEN AND

THIRTEEN.

NOTES:

1. Master reset overrides load data and clock inputs.

2. When counting up, clock-down input must be high.

When counting down, clock-up input must be high.

CPU OR CPD

INPUT LEVEL

INPUT LEVEL

TCU OR TCD

CPU OR CPD

INPUT LEVEL

INPUT LEVEL

INPUT LEVEL

CPU OR CPD

Pn

PL

MR

CPU OR CPD

INPUT LEVEL

INPUT LEVEL

CD74HC192, CD74HC193, CD74HCT193