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CDC2536 Datasheet(PDF) 6 Page - Texas Instruments

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Part # CDC2536
Description  3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
PDF  10 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDC2536 Datasheet(HTML) 6 Page - Texas Instruments

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CDC2536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS377D – APRIL 1994 – REVISED OCTOBER 1998
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
f lk
Clock frequency
When VCO is operating at four times the CLKIN frequency
25
50
MHz
fclock
Clock frequency
When VCO is operating at double the CLKIN frequency
50
100
MHz
Duty cycle, CLKIN
40%
60%
†
After SEL
50
Stabilization time†
After OE
↓
50
µs
Stabilization time†
After power up
50
µs
After CLKIN
50
† Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 15 pF (see Note 4 and Figures 1, 2 and 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
fmax
100
MHz
Duty cycle
Y
45%
55%
tphase error‡
CLKIN
↑
Y
↑
–500
+500
ps
tjitter (RMS)
CLKIN
↑
Y
↑
200
ps
tsk(o)‡
0.5
ns
tsk(pr)‡
1
ns
tr
1.4
ns
tf
1.4
ns
‡ The propagation delay, tphase error, is dependent on the feedback path from any output to FBIN. The tphase error, tsk(o), and tsk(pr)specfications
are only valid for equal loading of all outputs.
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT FOR OUTPUTS
CL = 15pF
(see Note A)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tphase error
1.5 V
1.5 V
3 V
0 V
1.5 V
VOH
VOL
Input
0.8 V
2 V
tr
tf
0.8 V
2 V
Output
500
W
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤ 100 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms



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